The present invention relates generally to semiconductor memory devices and, more particularly, to a method and apparatus for read bitline clamping for three-transistor (3T) gain cell DRAM devices.
Dynamic Random Access Memory (DRAM) devices commonly employ a one-transistor memory cell arrangement that includes an access transistor and a storage capacitor. The information is stored in the storage capacitor in the form of an electrical charge that represents a logical level, 0 or 1. This information can be read out from or written to the cell by activating a wordline coupled to the access transistor via a word line. During a read operation, the electrical charge stored in the storage capacitor is transferred to a bitline and sensed by sense amplifier circuitry. During a write operation, electrical charge is added to or removed from the storage capacitor by the bitline.
Since the storage density increases from generation to generation of memory, the required surface area of the one-transistor memory cell must be reduced from generation to generation. This leads to fundamental technological and physical problems (particularly for performance), because the threshold voltage of an access transistor in a one-transistor memory cell is not reduced due to the device leakage. Yet, the operation voltage should be reduced to guarantee the device reliability.
This problem is avoided in one approach by an alternative DRAM cell arrangement wherein so-called xe2x80x9cgainxe2x80x9d cells are used as storage cells. Like the one-transistor/storage capacitor cell, data is also stored in gain cells in the form of an electrical charge. However, the electrical charge in a gain cell is not directly coupled to a bitline, but rather is stored in a gate electrode of a gain transistor (thereby controlling the conductivity of that transistor), for which purpose a very small amount of electrical charge is sufficient. Because gain cells do not require an electrical charge for signal storage, the capacitance of the cell can be reduced significantly. This results in a relatively short time constant as compared to the conventional one transistor memory cell with a large storage capacitance. In addition, as long as the storage node voltage is higher than the threshold voltage of the gain transistor, the device is turned on, further improving performance.
In a gain cell 100 having a three-transistor (3T) configuration such as shown in FIG. 1, the electrical charge is stored in a first gate electrode of a first transistor 114 (i.e., a gain transistor). The writing or storage of the electrical charge therein occurs with the aid of a second transistor 116 (i.e., a write access transistor). In particular, the gate electrode N of the gain transistor 114 is connected to one of the source/drain regions of the write access transistor 116, while the other source/drain region of the write access transistor 116 is connected to a write bitline WBL. During a write operation to the gain cell 100, the gate electrode of the write access transistor 116 is activated via an appropriate signal on a write wordline WWL. This allows the gate electrode N of the gain transistor 114 to be coupled to the write bitline WBL through transistor 116. The amount of electrical charge stored in the node N (and thus the data bit information stored in the gain transistor gate electrode) is determined by the voltage present on the write bitline when the write wordline is activated. The gate capacitor of the gain transistor 114 keeps sufficient electrical charge at storage node N. Similar to a conventional one-transistor DRAM, the storage node N should be periodically refreshed to rewrite (maintain) the voltage at the node N before the charge has been lost completely.
The readout of stored information in a 3T gain cell occurs with the aid of a third transistor 112 (i.e., a read access transistor). One of the source/drain regions of the gain transistor 114 is connected to one of the source/drain regions of the read access transistor 112, while the other of the source/drain regions of the gain transistor 114 is connected to either VDD or ground, depending upon the type of the cell transistors (PFET or NFET). In addition, the other of the source/drain regions of the read access transistor is connected to a read bitline RBL. The read bitline RBL is precharged to either VDD or ground, again depending upon the type of the cell transistors (PFET or NFET). For example, in a 3T gain cell having NFET transistors, the read bitline is precharged to VDD, and the other of the source/drain regions of the gain transistor is connected to ground, as shown in FIG. 1. During a read operation, the gate electrode of the read access transistor 112 is actuated via a read wordline RWL. This allows the drain of gain transistor 114 to be coupled to the read bitline RBL through the transistor 112. The read bit line is therefore determined by the conductance through the series combination of the read transistor 112 and gain transistor 114 coupling to ground.
In addition, FIG. 1 illustrates aPFET pull-up transistor 118 configured as a precharge device that dynamically precharges the read bitline RBL to the supply voltage VDD. Thus, if the storage node N maintains a xe2x80x9c1xe2x80x9d data bit therein, the read bitline RBL is discharged down from VDD since both transistors 112 and 114 are conductive. On the other hand, if the storage node N maintains a xe2x80x9c0xe2x80x9d data bit therein, the read bitline RBL is not discharged from the precharge voltage since the gain transistor 114 is non-conductive. The presence of a RBL voltage swing (i.e., reading xe2x80x9c1xe2x80x9d data) is detected by appropriate sense amplifier circuitry (not shown), which is well known and therefore not discussed in further detail hereinafter. After the read operation of the cell data is completed, the RBL precharge device 118 is turned on (i.e., the signal on precharge line PRE goes low) to restore the read bitline voltage to VDD.
One problem associated with the above described cell configuration results during a read operation of a cell having a xe2x80x9c1xe2x80x9d stored therein (using NFET transistors in the cell). In this case, the activation of the read wordline, combined with the gate of the gain transistor being activated as a result of storing a xe2x80x9c1xe2x80x9d, causes the read bitline to be discharged toward ground. In order to provide desired fast access speed, a rapid RBL swing is needed to sense the xe2x80x9c1xe2x80x9d data (it is noted that no bitline swing occurs when reading a xe2x80x9c0xe2x80x9d since the gain transistor is not conductive). However, if the read bitline swing is too fast, the voltage on the read bitline goes to ground, thereby resulting a longer restore time to return the read bitline voltage back to VDD. As also mentioned previously, the circuit of FIG. 1 provides a fast access speed for reading xe2x80x9c1xe2x80x9d data as a result of the fast RBL swing.
A typical known solution is to include a read bitline clamp device to limit a read bitline swing. Without this clamp device, the voltage on read bitline RBL (in worst case) goes to ground. This condition results in a longer restore time for returning the RBL voltage back to VDD. If the clamp device is implemented by substituting it for a dynamically controlled precharge device, the restore time is improved, but at the cost of a slower read bitline swing. This is due to the fact that a read access transistor needs to be able drive the read bitline RBL to ground. However, some of the current is also used for the clamp device coupling to VDD. In addition, the clamp device must be laid out for each column, which increases the silicon area. Furthermore, the conventional use of a separate clamping device does not allow for xe2x80x9ctrackingxe2x80x9d of variations in certain memory cell transistor and voltage parameters. Thus, it is desirable to have a gain transistor DRAM cell configuration that has both a fast read bitline voltage and an improved restore time, while also allowing for device process tracking and without sacrificing device real estate area.
The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a dynamic random access memory (DRAM) storage device. In an exemplary embodiment, a storage cell has a plurality of transistors arranged in a gain cell configuration, the gain cell coupled to a read bitline and a write bitline. A dummy cell is configured as a clamping device for the read bitline, wherein the dummy cell opposes a read bitline voltage swing during a read operation of the storage cell.
In another aspect, a method for clamping a read bitline of a gain access dynamic random access memory (DRAM) device having a plurality of storage cells associated therewith includes configuring a dummy cell as a clamping device for the read bitline, wherein the dummy cell opposes a read bitline voltage swing during a read operation of one of the plurality of storage cells.